View STA8088GA_8295684.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

for further information contact your local stmicroelectronics sales office. september 2014 docid022679 rev 5 1/17 STA8088GA automotive grade gps/galileo/glonass/qzss receiver data brief features ? stmicroelectronics ? 3 rd generation positioning receiver with 32 tracking channels and 2 fast acquisition channels compatible with gps, galileo and glonass systems ? embedded rf front-end with separate gps/galieo/qzss and glonass if outputs ? embedded low noise amplifier ? -162 dbm indoor sensitivity (tracking mode) ? fast ttff <1 s in hot start and 35s in cold start ? high performance arm946 mcu (up to 208 mhz) ? 256 kbyte embedded sram ? real time clock (rtc) circuit ? 32-bit watch-dog timer ? 2 uarts ? 1 i 2 c master/slave interface ? 1 external sqi flash interface ? usb2.0 dual-role full speed (12 mhz) with integrated physical layer transceiver ? 2 controller area network (can) ? 3 channels adc (10 bits) ? 3 embedded 1.8 v voltage regulators ? i/o level selectable 1.8 v or 3.3 v ? operating condition: ?v dd12 : 1.2 v 10% ?v dd18/rf18 : 1.8 v 5% ?v lpvr 1.62 v to 3.6 v ?v ddio : 1.8 v 5%; 3.3 v 10% ? st automotive grade compliant ? package: ? vfqfpn56 (7x7x0.85 mm) 0.4 mm pitch ? ambient temperature range: -40/+85c description STA8088GA is a single die standalone positioning receiver ic working on multiple constellations (gps/galileo/glonass/qzss). the device is compliant with st automotive grade which in addition to aec-q100 qualification includes a set of production flow methodology targeting zero defect per million. STA8088GA, fulfilling high quality and service level automotive market requirements, is the ideal solution for in-dash navigation and oem telematic application. the device is offered with a complete gnss firmware which performs all gnss operations including tracking, acquisition, navigation and data output. vfqfpn56 www.st.com
contents STA8088GA 2/17 docid022679 rev 5 contents 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 vfqfpn56 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3 power supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 main function pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.5 test/emulated dedicated pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.6 rf front-end pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.7 port 0 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.8 port 1 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3 package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 ecopack ? packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 vfqfpn56 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
docid022679 rev 5 3/17 STA8088GA list of tables 3 list of tables table 1. power supply pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 2. main function pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 3. test/emulated dedicated pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 4. rf front-end pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 5. port 0 pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 6. port 1 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 7. vfqfpn56 7 x 7 x 0.85 mm package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 8. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
list of figures STA8088GA 4/17 docid022679 rev 5 list of figures figure 1. STA8088GA system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. vfqfpn56 connection diagram - automotive grade (with can) (bottom view) . . . . . . . . . 7 figure 3. vfqfpn56 connection diagram - no can (bottom view). . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. vfqfpn56 package dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 5. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
docid022679 rev 5 5/17 STA8088GA overview 16 1 overview STA8088GA is a highly integrated system-on-chip device designed for positioning systems applications. it combines the high performance of arm946 microprocessor with embedded enhanced peripherals and i/o capabilities with st next generation triple-constellation positioning engine. the rf front-end and base band processors are able to support gps/galileo and glonass navigation systems. the device is offered with a complete firmware which performs all positioning operations including tracking, acquisition, navigation and data output with no need of external memories. it also provides clock generation via pll, backup logic with real time clock and it supports usb2.0 standard at full speed, (12 mbps) with on-chip phy. STA8088GA is software compatible with the arm processor family. the device is power supplied with 1.8 v and uses three on-chip voltage regulators to internally supply the rf front-end, core logic and the backup logic. in order to reduce the power consumption the chips can be directly powered with 1.2v bypassing the embedded voltage regulators which will be put in power down mode. i/o lines are compatible with 1.8v and 3.3v. STA8088GA, using stmicroelectronics cmosrf technology, is housed in vfqfpn56 (7 x 7 x 0.85 mm) package. STA8088GA is compliant with st automotive grade which in addition to aec-q100 qualification includes a set of production flow methodology targeting zero defect per million. STA8088GA, fulfilling high quality and service level automotive market requirements, is the ideal solution for in-dash navigation and oem telematic application.
pin description STA8088GA 6/17 docid022679 rev 5 2 pin description 2.1 block diagram figure 1. STA8088GA system block diagram bk_domain sqi if usb if vic rom 16kb ahb dcreg osci32 thsens saradc ad10sa1m_18 osci32 osci32_lj_1v8 pwr, rst & clk ctrl iso cell i2c ssp uart2 rx - tx regmap apb bridge2 uart1 rx - tx adc mtu gpio eft wd apb arm 946 i-cache 16kb d-cache 8kb high speed i - tcm 64kb 64khigh speed d ? tcm 8 apb bridge1 sys ctrl rtc apb ram 8kb g3 base band glonass if galgps if 2 fast acq channel 32 trk channels mux acq rams apb bridge dc_ln_1v8to1v2 hpreg lpreg bkreg clock_gen ckx2 pll pg_650x frc_dpll riosc47 test controller ios jtag g3rf ip 1.8v 1.2v dcreg spi if osci 26mhz rf section lna section adc galgps adc glonass i/d switchable tcm 8x16kb gapgcft00543 can1 can0
docid022679 rev 5 7/17 STA8088GA pin description 16 2.2 vfqfpn56 pin configuration figure 2. vfqfpn56 connection diagram - automotive grade (with can) (bottom view) 4 567q 9''b095 73b,)b3 73b,)b1 95)b5)$'& /1$b,1 *1'b/1$ /1$b287 95)287b5)95 95)b5)95 95)b/1$ 64,b6,2%227b 3 64,b6,23 8 $57b7;%227b 3 8$57b5;3 *3,23 $'&b,1 $'&b,1 $'&b,1 9''b095 57&b;72 9''b/395 57&b;7, 64,b&(q3 9''b,25 64,b6,2623 64,b6,26,3 64,b&/.3 9''b095 86%b'38$57b7; 86%b'08$57b5; 7'2 9''b,25 7', 7&. 95)b5)$ 5)$b,1 95)b0,; 95)b,) 95)b5)9&2 ;7$/b,1 ;7$/b287 9''b/395 9''b095 67'%<q :$.(83 &$15;,&b6&/. 3 67'%<287 9''b095 &$17; &$17;,&b6' 3 &$15; 9''b,25 *3,23 (3 706 567q ("1($'5
pin description STA8088GA 8/17 docid022679 rev 5 figure 3. vfqfpn56 connection diagram - no can (bottom view) 2.3 power supply pins 4 567q 9''b095 73b,)b3 73b,)b1 95)b5)$'& /1$b,1 *1'b/1$ /1$b287 95)287b5)95 95)b5)95 95)b/1$ 64,b6,2%227b3 64,b6,23 8$57b7;%227b 3 8$57b5; 3 *3,23 $'&b,1 $'&b,1 $'&b,1 9''b095 57&b;72 9''b/395 57&b;7, 64,b&(q3 9''b,25 64,b6,2623 64,b6,26,3 64,b&/.3 9''b095 86%b'38$57b7; 86%b'08$57b5; 7'2 9''b,25 7', 7&. 95)b5)$ 5)$b,1 95)b0,; 95)b,) 95)b5)9&2 ;7$/b,1 ;7$/b287 9''b/395 9''b095 67'%<q :$.(83 ,&b6&/. 3 67'%<287 9''b095 1& ,&b6' 3 1& 9''b,25 *3,23 (3 706 567q ("1($'5 table 1. power supply pins symbol i/o functions vfqfn56 vdd18_mvr[1,2] pwr digital supply voltage for main voltage regulator (1.8 v) 31,4 vdd12_mvr[1,2,3] pwr digital supply voltage for core circuitry (1.2 v). when using the mvr, this pin shall not be driven by an external voltage supply, but a capacitance shall be connected between these pins and gnd to guarantee on-chip voltage stability. 22,47,30 vdd_lpvr pwr digital supply voltage for low power voltage regulator (1.62 - 3.6 v) 29
docid022679 rev 5 9/17 STA8088GA pin description 16 2.4 main function pins vdd12_lpvr pwr digital supply voltage for backup logic (1.2 v). when using the lpvr, this pin shall not be driven by an external voltage supply, but a capacitance shall be connected between these pins and gnd to guarantee on-chip voltage stability. 21 vdd_ior1 pwr digital supply voltage for i/o ring 1 (1.8 or 3.3 v) 44 vdd_ior3 pwr digital supply voltage for i/o ring 3 (1.8 v) 45 vdd_ior5 pwr digital supply voltage for i/o ring 5 (3.3 v) 52 vrf18_rfvr pwr analog supply voltage for rf voltage regulator (1.8 v) 13 vrf12out_rfvr pwr rf voltage regulator 1.2 v output 12 vrf12_lna pwr analog supply voltage for lna (1.2 v) 8 vrf12_rfa pwr analog supply voltage for rfa (1.2 v) 14 vrf12_mix pwr analog supply voltage for mixer (1.2 v) 16 vrf12_if pwr analog supply voltage for if (1.2 v) 17 vrf12_rfvco pwr analog supply voltage for vco (1.2 v) 18 vrf12_rfadc pwr analog supply voltage for rf adc (1.2 v) 7 gnd_lna gnd analog supply ground for lna 10 gnd gnd analog and digital supply ground ep table 1. power supply pins (continued) symbol i/o functions vfqfn56 table 2. main function pins symbol i/o voltage i/o functions vfqfpn56 stdbyn 1.2v i when low, the chip is forced in standby mode - all pins in high impedance except the ones powered by backup supply 24 stdbyout 1.2v o when low, indicates the chip is in standby mode. 23 rstn (1) 1.2v i reset input with schmitt-trigger characteristics and noise filter. 25 wakeup (2) 1.2v i wakeup from standby mode 26 rtc_xti 1.5v (max) i input of the 32khz oscillator amplifier circuit and input of the internal real time clock circuit. 27 rtc_xto 1.5v (max) o output of the oscillator amplifier circuit. 28 adc_in[1,5,8] 1.4v ? 0 typ range i adc analog input [1,5,8] 32,33, 34 usb_dp/uart1_tx vdd_ior5 usb/o usb d+ signal / uart1 tx data 48 usb_dm/uart1_rx vdd_ior5 usb/i usb d- signal / uart1 rx data 49
pin description STA8088GA 10/17 docid022679 rev 5 2.5 test/emulated dedicated pins 2.6 rf front-end pins 2.7 port 0 pins port 0 consists of a 32-bit bidirectional i/o port (only 3-bit are used in STA8088GA). it can be either used as general purpose input or output port, or configured according to the associated alternate functions. can0tx (3) vdd_ior5 o can0 - transmit data output 51 can0rx (3) vdd_ior5 i can0 - receive data input 54 1. when rstn is de-asserted, pin wakeup must be low. 2. the wakeup pulse must be longer than 500 s. 3. only for automotive grade devices (STA8088GA, sta8088a). table 2. main function pins (continued) symbol i/o voltage i/o functions vfqfpn56 table 3. test/emulated dedicated pins symbol i/o voltage i/o functions vfqfpn56 tdo vdd_ior5 o jtag test data out 50 tdi vdd_ior5 i jtag test data in 53 tck vdd_ior5 i jtag test clock 56 tms vdd_ior5 i jtag test mode select 2 trstn (1) vdd_ior5 i jtag test circuit reset 3 tp_if_p vrf12_if o diff. test point for if ? positive 5 tp_if_n vrf12_if o diff. test point for if ? negative 6 1. if jtag interface is not used, pin trstn must be asserted low. table 4. rf front-end pins symbol i/o voltage i/o functions vfqfpn56 lna_in vrf12_lna i low noise amplifier input 9 lna_out vrf12_lna o low noise amplifier output 11 rfa_in vrf12_rfa i rf amplifier input 15 xtal_in vrf12_rfdig i input side of crystal oscillator or tcxo input 19 xtal_out vrf12_rfdig o output side of crystal oscillator 20
docid022679 rev 5 11/17 STA8088GA pin description 16 2.8 port 1 pins port 1 consists of a 32-bit bidirectional i/o port (only9-bit are used in STA8088GA). it can be either used as general purpose input or output port, or configured according to the associated alternate functions. table 5. port 0 pins symbol i/o voltage i/o mode functions vfqfpn56 p0.0 vdd_ior1 io default gpio.0: general purpose io 35 i a pps_in: pulse per second input o b pps_out: pulse per second output p0.8 vdd_ior5 o default can1tx (1) : can1 transmit data output 55 io a gpio.8: general purpose io io b i2c_sd: i2c serial data p0.9 vdd_ior5 i default can1rx (1) : can1 receive data input 1 io a gpio.9: general purpose io o b i2c_sclk: i2c clock 1. only for automotive grade devices (STA8088GA, sta8088a). table 6. port 1 pins symbol i/o voltage i/o mode functions vfqfpn56 p1.0 vdd_ior1 o default sqi_cen: sqi flash chip enable 40 i/o a gpio32: general purpose i/o i/o b signggps: ggps 3bit coding output (sign) p1.1 vdd_ior1 o default sqi_clk: sqi flash clock 41 i/o a gpio33: general purpose i/o i/o b clock_ggps: ggps clock out p1.2 vdd_ior1 i/o default sqi_sio0/si: sqi flash data i/o 0 / ser. i 42 i/o a gpio34: general purpose i/o i/o b signgns: gns 3bit coding output (sign) p1.3 vdd_ior1 i/o default sqi_sio1/so: sqi flash data i/o 1 / ser. o 43 i/o a gpio35: general purpose i/o i/o b clock_gns: gns clock out p1.4 vdd_ior1 i default uart2_rx: uart 2 rx data 36 i/o a gpio36: general purpose i/o
pin description STA8088GA 12/17 docid022679 rev 5 p1.5 vdd_ior1 i/o default uart2_tx / boot_0: uart 2 tx data / arm boot 0 37 i/o a gpio37: general purpose i/o p1.6 vdd_ior1 i/o default sqi_sio2: sqi flash data i/o 2 38 i/o a gpio38: general purpose i/o p1.7 vdd_ior1 i/o default sqi_sio3/boot_1: sqi flash data i/o 3/armboot 1 39 i/o a gpio39: general purpose i/o p1.21 vdd_ior3 i/o a gpio53: general purpose i/o 46 table 6. port 1 pins (continued) symbol i/o voltage i/o mode functions vfqfpn56
docid022679 rev 5 13/17 STA8088GA package and packing information 16 3 package and packing information 3.1 ecopack ? packages in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. 3.2 vfqfpn56 package information table 7. vfqfpn56 7 x 7 x 0.85 mm package dimensions symbol min. typ. max common dimensions a 0.80 0.85 0.90 a1 0 0.01 0.05 a2 0.60 0.65 0.70 a3 0.20 ref b 0.15 0.20 0.25 d 7.00 bsc d1 6.75 bsc d2 5.0 5.1 5.2 e 7.00 bsc e1 6.75 bsc e2 5.0 5.1 5.2 e 0.40 bsc 0 12 l 0.30 0.40 0.50 n56 nd 14 ne 14 p 0.24 0.42 0.60
package and packing information STA8088GA 14/17 docid022679 rev 5 figure 4. vfqfpn56 package dimension ("1($'5
docid022679 rev 5 15/17 STA8088GA ordering information 16 4 ordering information figure 5. ordering information scheme packing gnss automotive grade tr = tape and reel = tray a = st automotive grade (with can) = aec-q100 (no can) g = gps/glonass/galileo/qzss = gps/qzss sal without flash sta8088 tr ga example code: family identifier
revision history STA8088GA 16/17 docid022679 rev 5 5 revision history table 8. document revision history date revision changes 17-jan-2012 1 initial release. 14-mar-2012 2 updated features list table 2: main function pins : ? usb_dp/uart1_tx, usb_dm/uart1_rx: updated i/o table 7: vfqfpn56 7 x 7 x 0.85 mm package dimensions : ? q, r: removed rows added table 8: vfqfpn56 8 x 8 x 0.85 mm package dimensions updated figure 5: ordering information scheme 16-sep-2013 3 updated disclaimer. 14-apr-2014 4 updated description . 23-sep-2014 5 updated features list updated chapter 1: overview table 2: main function pins : ? rstn, wateup: added note table 3: test/emulated dedicated pins : ? trstn: added note removed table 8: vfqfpn56 8 x 8 x 0.85 mm package dimensions updated figure 5: ordering information scheme
docid022679 rev 5 17/17 STA8088GA 17 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2014 stmicroelectronics ? all rights reserved

▲Up To Search▲

Price & Availability of STA8088GA

	To Download STA8088GA Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .